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PCF8576D
Universal LCD driver for low multiplex rates
Rev. 7 -- 18 December 2008 Product data sheet
1. General description
The PCF8576D is a peripheral device which interfaces to almost any Liquid Crystal Display (LCD) with low multiplex rates. It generates the drive signals for any static or multiplexed LCD containing up to four backplanes and up to 40 segments. It can be easily cascaded for larger LCD applications. The PCF8576D is compatible with most microprocessors or microcontrollers and communicates via a two-line bidirectional I2C-bus. Communication overheads are minimized by a display RAM with auto-incremented addressing, by hardware subaddressing and by display memory switching (static and duplex drive modes). AEC-Q100 compliant (PCF8576DH/2) for automotive applications.
2. Features
I I I I I Single chip LCD controller and driver Selectable backplane drive configuration: static or 2, 3, 4 backplane multiplexing Selectable display bias configuration: static, 12 or 13 Internal LCD bias generation with voltage-follower buffers 40 segment drives: N Up to twenty 7-segment numeric characters N Up to ten 14-segment alphanumeric characters N Any graphics of up to 160 elements 40 x 4-bit RAM for display data storage Auto-incremented display data loading across device subaddress boundaries Display memory bank switching in static and duplex drive modes Versatile blinking modes Independent supplies possible for LCD and logic voltages Wide power supply range: from 1.8 V to 5.5 V Wide logic LCD supply range: N From 2.5 V for low-threshold LCDs N Up to 6.5 V for guest-host LCDs and high-threshold twisted nematic LCDs Low power consumption 400 kHz I2C-bus interface May be cascaded for large LCD applications (up to 2560 elements possible) No external components Compatible with chip-on-glass and chip-on-board technology Manufactured in silicon gate CMOS process
I I I I I I I
I I I I I I
NXP Semiconductors
PCF8576D
Universal LCD driver for low multiplex rates
3. Ordering information
Table 1. Ordering information Package Name PCF8576DH/2 PCF8576DT/2 PCF8576DU/DA/2 TQFP64 TSSOP56 PCF8576DU/DA Description plastic thin quad flat package, 64 leads; body 10 x 10 x 1.0 mm plastic thin shrink small outline package, 56 leads; body width 6.1 mm wire bond die; 59 bonding pads; 2.26 x 2.01 x 0.38 mm[1] mm[1] Version SOT357-1 SOT364-1 PCF8576DU/DA PCF8576DU/2DA Type number
PCF8576DU/2DA/2 PCF8576DU/2DA bare die; 59 bumps; 2.26 x 2.01 x 0.40
[1] [1] Chips in tray. Chips with bumps in tray.
4. Marking
Table 2. Marking codes Marking code PCF8576DH PCF8576DT PC8576D-2 PC8576D-2 Type number PCF8576DH/2 PCF8576DT/2 PCF8576DU/DA/2 PCF8576DU/2DA/2
PCF8576D_7
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Product data sheet
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NXP Semiconductors
PCF8576D
Universal LCD driver for low multiplex rates
5. Block diagram
BP0 BP2 BP1 BP3 S0 to S39
40
VLCD
BACKPLANE OUTPUTS LCD VOLTAGE SELECTOR DISPLAY CONTROLLER
DISPLAY SEGMENT OUTPUTS
DISPLAY REGISTER
LCD BIAS GENERATOR VSS CLK SYNC
OUTPUT BANK SELECT AND BLINK CONTROL
CLOCK SELECT AND TIMING
BLINKER TIMEBASE
PCF8576D
DISPLAY RAM 40 x 4-BIT
OSC VDD SCL SDA
OSCILLATOR
POWER-ON RESET
COMMAND DECODER
WRITE DATA CONTROL
DATA POINTER AND AUTO INCREMENT
INPUT FILTERS
I2C-BUS CONTROLLER
SUBADDRESS COUNTER
SA0
A0
A1
A2
001aai900
Fig 1.
Block diagram of PCF8576D
PCF8576D_7
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Product data sheet
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PCF8576D
Universal LCD driver for low multiplex rates
6. Pinning information
6.1 Pinning
61 S30 60 S29 59 S28 58 S27 57 S26 56 S25 55 S24 54 S23 53 S22 52 S21 51 S20 50 S19 49 S18 48 n.c. 47 S17 46 S16 45 S15 44 S14 43 S13 42 S12 41 S11 40 S10 39 S9 38 S8 37 S7 36 S6 35 S5 34 S4 33 n.c. A1 17 A2 18 SA0 19 VSS 20 VLCD 21 n.c. 22 n.c. 23 n.c. 24 BP0 25 BP2 26 BP1 27 BP3 28 S0 29 S1 30 S2 31 S3 32
001aaf645
64 S33 n.c. S34 S35 S36 S37 S38 S39 n.c. n.c. 1 2 3 4 5 6 7 8 9
63 S32
62 S31
PCF8576DH
SDA 10 SCL 11 SYNC 12 CLK 13 VDD 14 OSC 15 A0 16
Top view. For mechanical details, see Figure 24.
Fig 2.
Pinning diagram for PCF8576DH/2
PCF8576D_7
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Product data sheet
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PCF8576D
Universal LCD driver for low multiplex rates
BP2 BP1 BP3 S0 S1 S2 S3 S4 S5
1 2 3 4 5 6 7 8 9
56 BP0 55 VLCD 54 VSS 53 SA0 52 A2 51 A1 50 A0 49 OSC 48 VDD 47 CLK 46 SYNC 45 SCL 44 SDA 43 S39 42 S38 41 S37 40 S36 39 S35 38 S34 37 S33 36 S32 35 S31 34 S30 33 S29 32 S28 31 S27 30 S26 29 S25
001aaf646
S6 10 S7 11 S8 12 S9 13 S10 14 S11 15 S12 16 S13 17 S14 18 S15 19 S16 20 S17 21 S18 22 S19 23 S20 24 S21 25 S22 26 S23 27 S24 28
PCF8576DT
Top view. For mechanical details, see Figure 25.
Fig 3.
Pinning diagram for PCF8576DT/2
PCF8576D_7
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PCF8576D
Universal LCD driver for low multiplex rates
S17
S16
S15
S14
S13
S12
S11
S10
S9
S8
S7
S6
S5
35
34
33
32
31
30
29
28
27
26
25
24
23
22
S4
21
S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33
S3 S2 S1 S0 BP3 BP1 BP2 BP0
36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51
20 19 18 17 16 15 14
PCF8576DU
13
VLCD
12
VSS
11 10 9
SA0 A2 A1
52
53
54
55
56
57
58
59
1
2
3
4
5
6
7
OSC
SDA
SDA
SDA
SCL
SCL
SYNC
CLK
VDD
S34
S35
S36
S37
S38
S39
C2
A0
8
C1
001aag424
(c) NXP B.V. 2008. All rights reserved.
Top view. C1 and C2 are alignment marks. For mechanical details, see Figure 26 and Figure 27.
Fig 4.
Pinning diagram for PCF8576DUx
PCF8576D_7
Product data sheet
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NXP Semiconductors
PCF8576D
Universal LCD driver for low multiplex rates
6.2 Pin description
Table 3. Symbol SDA SCL CLK VDD SYNC OSC A0 to A2 SA0 VSS VLCD BP0, BP2, BP1, BP3 S0 to S39 n.c. Pin description Pin PCF8576DH/2 10 11 13 14 12 15 16 to 18 19 20 21 25 to 28 29 to 32, 34 to 47, 49 to 64, 2 to 7 1, 8, 9, 22 to 24, 33, 48 PCF8576DT/2 44 45 47 48 46 49 50 to 52 53 54 55 56, 1, 2, 3 4 to 43 PCF8576DUx 1, 58 and 59 2 and 3 5 6 4 7 8 to 10 11 12[1] 13 14 to 17 18 to 57 I2C-bus serial data input and output I2C-bus serial clock input external clock input or output supply voltage cascade synchronization input or output internal oscillator enable input subaddress inputs I2C-bus address input; bit 0 ground supply voltage LCD supply voltage LCD backplane outputs LCD segment outputs not connected Description
[1]
The substrate (rear side of the die) is wired to VSS but should not be electrically connected.
7. Functional description
The PCF8576D is a versatile peripheral device designed to interface any microprocessor or microcontroller with a wide variety of LCDs. It can directly drive any static or multiplexed LCD containing up to four backplanes and up to 40 segments. The possible display configurations of the PCF8576D depend on the number of active backplane outputs required. A selection of display configurations is shown in Table 4. All of these configurations can be implemented in the typical system shown in Figure 5.
Table 4. Display configurations 7-segment numeric Indicator symbols 20 15 10 5 14-segment numeric Characters Indicator symbols 10 8 5 2 20 8 10 12 160 dots (4 x 40) 120 dots (3 x 40) 80 dots (2 x 40) 40 dots (1 x 40) Dot matrix
Number of:
Backplanes Segments Digits 4 3 2 1 160 120 80 40 20 15 10 5
PCF8576D_7
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Product data sheet
Rev. 7 -- 18 December 2008
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PCF8576D
Universal LCD driver for low multiplex rates
VDD R
tr 2CB SDA SCL OSC
VDD
VLCD
40 segment drives
HOST MICROPROCESSOR/ MICROCONTROLLER
LCD PANEL (up to 160 elements)
PCF8576D
4 backplanes
A0 VSS
A1
A2
SA0 VSS
mdb079
The resistance of the power lines must be kept to a minimum. For chip-on-glass applications, due to the Indium Tin Oxide (ITO) track resistance, each supply line must be routed separately between the chip and the connector.
Fig 5.
Typical system configuration
The host microprocessor or microcontroller maintains the 2-line I2C-bus communication channel with the PCF8576D. The internal oscillator is enabled by connecting pin OSC to pin VSS. The appropriate biasing voltages for the multiplexed LCD waveforms are generated internally. The only other connections required to complete the system are to the power supplies (VDD, VSS and VLCD) and the LCD panel chosen for the application.
7.1 Power-on reset
At power-on the PCF8576D resets to the following starting conditions:
* * * * * * * *
All backplane outputs are set to VLCD All segment outputs are set to VLCD The selected drive mode is: 1:4 multiplex with 13 bias Blinking is switched off Input and output bank selectors are reset The I2C-bus interface is initialized The data pointer and the subaddress counter are cleared Display is disabled
Data transfers on the I2C-bus must be avoided for 1 ms following power-on to allow the reset action to complete.
7.2 LCD bias generator
Fractional LCD biasing voltages are obtained from an internal voltage divider consisting of three impedances connected in series between VLCD and VSS. The middle resistor can be bypassed to provide a 12 bias voltage level for the 1:2 multiplex configuration. The LCD voltage can be temperature compensated externally using the supply to pin VLCD.
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PCF8576D
Universal LCD driver for low multiplex rates
7.3 LCD voltage selector
The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the selected LCD drive configuration. The operation of the voltage selector is controlled by the mode-set command (see Section 7.17) from the command decoder. The biasing configurations that apply to the preferred modes of operation, together with the biasing characteristics as functions of VLCD and the resulting discrimination ratios (D), are given in Table 5.
Table 5. LCD drive mode static Discrimination ratios Number of: Backplanes Levels 1 2 3 4 4 4 LCD bias V on ( RMS ) V off ( RMS ) V on ( RMS ) configuration -------------------------- ------------------------ D = -------------------------V LCD V off ( RMS ) V LCD static
1 2 1 3 1 3 1 3
0 0.354 0.333 0.333 0.333
1 0.791 0.745 0.638 0.577
2.236 2.236 1.915 1.732
1:2 multiplex 2 1:2 multiplex 2 1:3 multiplex 3 1:4 multiplex 4
A practical value for VLCD is determined by equating Voff(RMS) with a defined LCD threshold voltage (Vth), typically when the LCD exhibits approximately 10 % contrast. In the static drive mode a suitable choice is VLCD > 3Vth. Multiplex drive modes of 1:3 and 1:4 with 12 bias are possible but the discrimination and hence the contrast ratios are smaller.
1 Bias is calculated by ------------ , where the values for a are 1+a
a = 1 for 12 bias a = 2 for 13 bias The RMS on-state voltage (Von(RMS)) for the LCD is calculated with the equation
2 1 1 -- + ( n - 1 ) x ------------ 1 + a n ----------------------------------------------------------n
V on ( RMS ) =
V LCD
(1)
where VLCD is the resultant voltage at the LCD segment and where the values for n are n = 1 for static mode n = 2 for 1:2 multiplex n = 3 for 1:3 multiplex n = 4 for 1:4 multiplex The RMS off-state voltage (Voff(RMS)) for the LCD is calculated with the equation: V off ( RMS ) =
V LCD
a - ( 2a + n ) -------------------------------2 n x (1 + a)
2
(2)
Discrimination is the ratio of Von(RMS) to Voff(RMS) and is determined from the equation:
PCF8576D_7
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PCF8576D
Universal LCD driver for low multiplex rates (a + 1) + (n - 1) ------------------------------------------2 (a - 1) + (n - 1)
2
V on ( RMS ) ----------------------- = V off ( RMS )
(3)
Using Equation 3, the discrimination for an LCD drive mode of 1:3 multiplex with
1 1 2 bias 2 bias
is
3 = 1.732 and the discrimination for an LCD drive mode of 1:4 multiplex with
21 is ---------- = 1.528 . 3
The advantage of these LCD drive modes is a reduction of the LCD full scale voltage VLCD as follows:
* 1:3 multiplex (12 bias):V LCD =
6 x V off ( RMS ) = 2.449V off ( RMS )
) * 1:4 multiplex (12 bias): V LCD = ( 4 x 3 - = 2.309V off ( RMS ) ---------------------
3
These compare with V LCD = 3V off ( RMS ) when 13 bias is used. It should be noted that VLCD is sometimes referred as the LCD operating voltage.
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PCF8576D
Universal LCD driver for low multiplex rates
7.4 LCD drive mode waveforms
7.4.1 Static drive mode
The static LCD drive mode is used when a single backplane is provided in the LCD. The backplane (BPn) and segment drive (Sn) waveforms for this mode are shown in Figure 6.
Tfr VLCD BP0 VSS VLCD Sn VSS VLCD state 1 (on) state 2 (off) LCD segments
Sn+1
VSS (a) Waveforms at driver. VLCD
state 1
0V
-VLCD VLCD
state 2
0V
-VLCD (b) Resultant waveforms at LCD segment.
mgl745
(1) Vstate1(t) = VSn(t) - VBP0(t). (2) Von(RMS) = VLCD. (3) Vstate2(t) = VSn+1(t) - VBP0(t). (4) Voff(RMS) = 0 V.
Fig 6.
Static drive mode waveforms
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PCF8576D
Universal LCD driver for low multiplex rates
7.4.2 1:2 Multiplex drive mode
The 1:2 multiplex drive mode is used when two backplanes are provided in the LCD. This mode allows fractional LCD bias voltages of 12 bias or 13 bias as shown in Figure 7 and Figure 8.
Tfr VLCD BP0 VLCD / 2 VSS state 1 VLCD BP1 VLCD / 2 VSS VLCD Sn VSS VLCD state 2 LCD segments
Sn+1
VSS (a) Waveforms at driver. VLCD VLCD / 2 state 1 0V -VLCD / 2 -VLCD VLCD VLCD / 2 state 2 0V -VLCD / 2 -VLCD (b) Resultant waveforms at LCD segment.
mgl746
(1) Vstate1(t) = VSn(t) - VBP0(t). (2) Von(RMS) = 0.791VLCD. (3) Vstate2(t) = VSn+1(t) - VBP1(t). (4) Voff(RMS) = 0.354VLCD.
Fig 7.
Waveforms for the 1:2 multiplex drive mode with 12 bias
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PCF8576D
Universal LCD driver for low multiplex rates
Tfr VLCD BP0 2VLCD / 3 VLCD / 3 VSS VLCD BP1 2VLCD / 3 VLCD / 3 VSS VLCD Sn 2VLCD / 3 VLCD / 3 VSS VLCD 2VLCD / 3 VLCD / 3 VSS (a) Waveforms at driver. VLCD 2VLCD / 3 VLCD / 3 state 1 0V -VLCD / 3 -2VLCD / 3 -VLCD VLCD 2VLCD / 3 VLCD / 3 state 2 0V -VLCD / 3 -2VLCD / 3 -VLCD (b) Resultant waveforms at LCD segment.
mgl747
LCD segments
state 1 state 2
Sn+1
(1) Vstate1(t) = VSn(t) - VBP0(t). (2) Von(RMS) = 0.745VLCD. (3) Vstate2(t) = VSn+1(t) - VBP1(t). (4) Voff(RMS) = 0.333VLCD.
Fig 8.
Waveforms for the 1:2 multiplex drive mode with 13 bias
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PCF8576D
Universal LCD driver for low multiplex rates
7.4.3 1:3 Multiplex drive mode
When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies (see Figure 9).
Tfr VLCD BP0 2VLCD / 3 VLCD / 3 VSS VLCD 2VLCD / 3 VLCD / 3 VSS VLCD 2VLCD / 3 VLCD / 3 VSS VLCD Sn 2VLCD / 3 VLCD / 3 VSS VLCD Sn+1 2VLCD / 3 VLCD / 3 VSS VLCD Sn+2 2VLCD / 3 VLCD / 3 VSS (a) Waveforms at driver. VLCD 2VLCD / 3 VLCD / 3 state 1 0V -VLCD / 3 -2VLCD / 3 -VLCD VLCD 2VLCD / 3 VLCD / 3 state 2 0V -VLCD / 3 -2VLCD / 3 -VLCD state 1 state 2 LCD segments
BP1
BP2
(b) Resultant waveforms at LCD segment.
mgl748
(1) Vstate1(t) = VSn(t) - VBP0(t). (2) Von(RMS) = 0.638VLCD. (3) Vstate2(t) = VSn+1(t) - VBP1(t). (4) Voff(RMS) = 0.333VLCD.
Fig 9.
Waveforms for the 1:3 multiplex drive mode with 13 bias
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PCF8576D
Universal LCD driver for low multiplex rates
7.4.4 1:4 Multiplex drive mode
When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies (see Figure 10).
Tfr VLCD BP0 2VLCD / 3 VLCD / 3 VSS VLCD 2VLCD / 3 VLCD / 3 VSS VLCD BP2 2VLCD / 3 VLCD / 3 VSS VLCD 2VLCD / 3 VLCD / 3 VSS VLCD 2VLCD / 3 VLCD / 3 VSS VLCD 2VLCD / 3 VLCD / 3 VSS VLCD state 1 state 2 LCD segments
BP1
BP3
Sn
Sn+1
Sn+2
2VLCD / 3 VLCD / 3 VSS VLCD 2VLCD / 3 VLCD / 3 VSS (a) Waveforms at driver. VLCD 2VLCD / 3 VLCD / 3
Sn+3
state 1
0V -VLCD / 3 -2VLCD / 3 -VLCD VLCD 2VLCD / 3 VLCD / 3
state 2
0V -VLCD / 3 -2VLCD / 3 -VLCD
(b) Resultant waveforms at LCD segment.
mgl749
(1) Vstate1(t) = VSn(t) - VBP0(t). (2) Von(RMS) = 0.577VLCD. (3) Vstate2(t) = VSn+1(t) - VBP1(t). (4) Voff(RMS) = 0.333VLCD.
Fig 10. Waveforms for the 1:4 multiplex drive mode with 13 bias
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PCF8576D
Universal LCD driver for low multiplex rates
7.5 Oscillator
7.5.1 Internal clock
The internal logic of the PCF8576D and its LCD drive signals are timed either by its internal oscillator or by an external clock. The internal oscillator is enabled by connecting pin OSC to pin VSS. If the internal oscillator is used, the output from pin CLK can be used as the clock signal for several PCF8576Ds in the system that are connected in cascade. After power-on, pin SDA must be HIGH to guarantee that the clock starts.
7.5.2 External clock
Pin CLK is enabled as an external clock input by connecting pin OSC to VDD. The LCD frame signal frequency is determined by the clock frequency (fclk). A clock signal must always be supplied to the device; removing the clock freezes the LCD in a DC state.
7.6 Timing
The PCF8576D timing controls the internal data flow of the device. This includes the transfer of display data from the display RAM to the display segment outputs. In cascaded applications, the correct timing relationship between each PCF8576D in the system is maintained by the synchronization signal at pin SYNC. The timing also generates the LCD frame signal whose frequency is derived from the clock frequency. The frame signal frequency is a fixed division of the clock frequency from either the internal or an external f clk clock: f fr = ------- . 24
7.7 Display register
The display latch holds the display data while the corresponding multiplex signals are generated. There is a one-to-one relationship between the data in the display latch, the LCD segment outputs and each column of the display RAM.
7.8 Segment outputs
The LCD drive section includes 40 segment outputs S0 to S39 which should be connected directly to the LCD. The segment output signals are generated in accordance with the multiplexed backplane signals and with data residing in the display latch. When less than 40 segment outputs are required, the unused segment outputs should be left open-circuit.
7.9 Backplane outputs
The LCD drive section includes four backplane outputs BP0 to BP3 which must be connected directly to the LCD. The backplane output signals are generated in accordance with the selected LCD drive mode. If less than four backplane outputs are required, the unused outputs can be left open-circuit. In the 1:3 multiplex drive mode, BP3 carries the same signal as BP1, therefore these two adjacent outputs can be tied together to give enhanced drive capabilities.
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PCF8576D
Universal LCD driver for low multiplex rates
In the 1:2 multiplex drive mode, BP0 and BP2, BP1 and BP3 all carry the same signals and may also be paired to increase the drive capabilities. In the static drive mode the same signal is carried by all four backplane outputs and they can be connected in parallel for very high drive requirements.
7.10 Display RAM
The display RAM is a static 40 x 4-bit RAM which stores LCD data. A logic 1 in the RAM bit-map indicates the on-state of the corresponding LCD segment; similarly, a logic 0 indicates the off-state. There is a one-to-one correspondence between the RAM addresses and the segment outputs, and between the individual bits of a RAM word and the backplane outputs. The display RAM bit map Figure 11 shows the rows 0 to 3 which correspond with the backplane outputs BP0 to BP3, and the columns 0 to 39 which correspond with the segment outputs S0 to S39. In multiplexed LCD applications the segment data of the first, second, third and fourth row of the display RAM are time-multiplexed with BP0, BP1, BP2 and BP3 respectively.
display RAM addresses (columns)/segment outputs (S) 0 0 display RAM bits 1 (rows)/ backplane outputs 2 (BP) 3
mbe525
1
2
3
4
35
36
37
38
39
Display RAM bit map showing direct relationship between RAM addresses and segment outputs; also between bits in a RAM word and the backplane outputs.
Fig 11. Display RAM bit map
When display data is transmitted to the PCF8576D, the display bytes received are stored in the display RAM in accordance with the selected LCD drive mode. The data is stored as it arrives and does not wait for an acknowledge cycle as with the commands. Depending on the current multiplex drive mode, data is stored singularly, in pairs, triplets or quadruplets. For example, in the 1:2 mode, the RAM data is stored every second bit. To illustrate the filling order, an example of a 7-segment numeric display showing all drive modes is given in Figure 12; the RAM filling organization depicted applies equally to other LCD types. With reference to Figure 12, in the static drive mode, the eight transmitted data bits are placed in row 0 of eight successive display RAM addresses. In the 1:2 mode, the eight transmitted data bits are placed in row 0 and 1 of four successive display RAM addresses. In the 1:3 mode, these bits are placed in row 0, 1 and 2 to three successive addresses, display RAM words, with bit 2 of the third address left unchanged. This last bit may, if necessary, be controlled by an additional transfer to this address but care should be taken to avoid overwriting adjacent data because always full bytes are transmitted; otherwise this segment should not be connected to the module.
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PCF8576D
Universal LCD driver for low multiplex rates
In the 1:4 mode, the eight transmitted data bits are placed in bits 0, 1, 2 and 3 of two successive display RAM addresses.
7.11 Data pointer
The addressing mechanism for the display RAM is realized using the data pointer. This allows the loading of an individual display data byte, or a series of display data bytes, into any location of the display RAM. The sequence commences with the initialization of the data pointer by the load-data-pointer command (see Section 7.17). Following this, an arriving data byte is stored at the display RAM address indicated by the data pointer in accordance with the filling order shown in Figure 12. After each byte is stored, the contents of the data pointer are automatically incremented by a value dependent on the selected LCD drive mode: eight (static drive mode), four (1:2 mode), three (1:3 mode) or two (1:4 mode). If an I2C-bus data access is terminated early then the state of the data pointer will be unknown. The data pointer should be re-written prior to further RAM access.
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Product data sheet Rev. 7 -- 18 December 2008
(c) NXP B.V. 2008. All rights reserved. PCF8576D_7
NXP Semiconductors
drive mode
LCD segments
LCD backplanes
display RAM filling order
transmitted display byte
Sn+2 Sn+3 Sn+4 static Sn+5 Sn+6 Sn 1:2 Sn+1
f e d f
a b
BP0 Sn+1 Sn bit/ BP DP
0 1 2 3
n c x x x
n+1 b x x x
n+2 a x x x
n+3 f x x x
n+4 g x x x
n+5 e x x x
n+6 d x x x
n+7
MSB
DP x x x
LSB g e d DP
g c
Sn+7
cbaf
BP0
a b g
n
n+1 f g x x
n+2 e c x x
n+3 d DP x x
multiplex
Sn+2 Sn+3 Sn+1
e d
BP1
c
bit/ BP
DP BP0
0 1 2 3
a b x x
MSB abf
LSB g e c d DP
a f g b
n
n+1
a d g x
n+2 f e x x
1:3
Sn+2
Sn bit/ BP
0 1 2 3 b DP c x
MSB b DP c a d g f
LSB
multiplex
e d
c
BP1 DP
BP2
Universal LCD driver for low multiplex rates
e
Sn 1:4
f
a b g
n
n+1 f e g d
BP0
BP2 bit/ BP
0 1 2 3 a c b DP
MSB a c b DP f
LSB egd
multiplex Sn+1
e d
c
BP1 DP
BP3
PCF8576D
001aag281
x = data bit unchanged.
19 of 52
Fig 12. Relationship between LCD layout, drive mode, display RAM filling order and display data transmitted over the I2C-bus
NXP Semiconductors
PCF8576D
Universal LCD driver for low multiplex rates
7.12 Output bank selector
The output bank selector selects one of the four bits per display RAM address for transfer to the display latch. The actual bit chosen depends on the selected LCD drive mode in operation and on the instant in the multiplex sequence.
* In 1:4 mode, all RAM addresses of bit 0 are selected, these are followed by the
contents of bit 1, bit 2 and then bit 3.
* In 1:3 mode, bits 0, 1 and 2 are selected sequentially * In 1:2 mode, bits 0 and 1 are selected * In static mode, bit 0 is selected
The SYNC signal resets these sequences to the following starting points:
* * * *
Bit 3 for 1:4 mode Bit 2 for 1:3 mode Bit 1 for 1:2 mode Bit 0 for static mode
The PCF8576D includes a RAM bank switching feature in the static and 1:2 drive modes. In the static drive mode, the bank-select command (see Section 7.17) may request the contents of bit 2 to be selected for display instead of the contents of bit 0. In 1:2 mode, the contents of bits 2 and 3 may be selected instead of bits 0 and 1. This gives the provision for preparing display information in an alternative bank and to be able to switch to it once it is assembled.
7.13 Input bank selector
The input bank selector loads display data into the display RAM in accordance with the selected LCD drive configuration. The bank-select command (see Section 7.17) can be used to load display data in bit 2 in static drive mode or in bits 2 and 3 in 1:2 mode. The input bank selector functions are independent of the output bank selector.
7.14 Subaddress counter
The storage of display data is determined by the contents of the subaddress counter. Storage is allowed to take place only when the contents of the subaddress counter agree with the hardware subaddress applied to A0, A1 and A2. The subaddress counter value is defined by the device-select command (see Section 7.17). If the contents of the subaddress counter and the hardware subaddress do not agree then data storage is inhibited but the data pointer is incremented as if data storage had taken place. The subaddress counter is also incremented when the data pointer overflows. The storage arrangements described lead to extremely efficient data loading in cascaded applications. When a series of display bytes are sent to the display RAM, automatic wrap-over to the next PCF8576D occurs when the last RAM address is exceeded. Subaddressing across device boundaries is successful even if the change to the next device in the cascade occurs within a transmitted character (such as during the 14th display data byte transmitted in 1:3 mode).
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PCF8576D
Universal LCD driver for low multiplex rates
The hardware subaddress must not be changed while the device is being accessed on the I2C-bus interface.
7.15 Blinker
The PCF8576D has a very versatile display blinking capability. The whole display can blink at a frequency selected by the blink-select command (see Section 7.17). Each blink frequency is a fraction of the clock frequency; the ratio between the clock frequency and blink frequency depends on the blink mode selected (see Table 6). An additional feature allows an arbitrary selection of LCD segments to blink in the static and 1:2 drive modes. This is implemented without any communication overheads by the output bank selector which alternates the displayed data between the data in the display RAM bank and the data in an alternative RAM bank at the blink frequency. This mode can also be implemented by the blink-select command (see Section 7.17). In the 1:3 and 1:4 drive modes, where no alternative RAM bank is available, groups of LCD segments can blink selectively by changing the display RAM data at fixed time intervals. The entire display can blink at a frequency other than the nominal blink frequency by sequentially resetting and setting the display enable bit E at the required rate using the mode-set command (see Section 7.17).
Table 6. off 1 2 3
[1]
Blinking frequencies[1] Normal operating mode ratio f clk --------768 f clk -----------1536 f clk -----------3072 Nominal blink frequency blinking off 2 Hz 1 Hz 0.5 Hz
Blink mode
Blink modes 1, 2 and 3 and the nominal blink frequencies 0.5 Hz, 1 Hz and 2 Hz correspond to an oscillator frequency (fclk) of 1536 Hz (see Section 11).
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PCF8576D
Universal LCD driver for low multiplex rates
7.16 Characteristics of the I2C-bus
The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.
7.16.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal (see Figure 13).
SDA
SCL data line stable; data valid change of data allowed
mba607
Fig 13. Bit transfer
7.16.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition - S. A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition - P (see Figure 14).
SDA
SDA
SCL S START condition P STOP condition
SCL
mbc622
Fig 14. Definition of START and STOP conditions
7.16.3 System configuration
A device generating a message is a transmitter, a device receiving a message is the receiver. The device that controls the message is the master and the devices which are controlled by the master are the slaves (see Figure 15).
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PCF8576D
Universal LCD driver for low multiplex rates
MASTER TRANSMITTER/ RECEIVER SDA SCL
SLAVE RECEIVER
SLAVE TRANSMITTER/ RECEIVER
MASTER TRANSMITTER
MASTER TRANSMITTER/ RECEIVER
mga807
Fig 15. System configuration
7.16.4 Acknowledge
The number of data bytes that can be transferred from transmitter to receiver between the START and STOP conditions is unlimited. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH-level signal on the bus that is asserted by the transmitter during which time the master generates an extra acknowledge related clock pulse. An addressed slave receiver must generate an acknowledge after receiving each byte. Also a master receiver must generate an acknowledge after receiving each byte that has been clocked out of the slave transmitter. The acknowledging device must pull-down the SDA line during the acknowledge clock pulse so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition (see Figure 16).
data output by transmitter not acknowledge data output by receiver acknowledge SCL from master S START condition clock pulse for acknowledgement
mbc602
1
2
8
9
Fig 16. Acknowledgement of the I2C-bus
7.16.5 I2C-bus controller
The PCF8576D acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or transmit data to an I2C-bus master receiver. The only data output from the PCF8576D are the acknowledge signals of the selected devices. Device selection depends on the I2C-bus slave address, on the transferred command data and on the hardware subaddress.
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PCF8576D
Universal LCD driver for low multiplex rates
In single device applications, the hardware subaddress inputs A0, A1 and A2 are normally tied to VSS which defines the hardware subaddress 0. In multiple device applications A0, A1 and A2 are tied to VSS or VDD in accordance with a binary coding scheme such that no two devices with a common I2C-bus slave address have the same hardware subaddress.
7.16.6 Input filters
To enhance noise immunity in electrically adverse environments, RC low-pass filters are provided on the SDA and SCL lines.
7.16.7 I2C-bus protocol
Two I2C-bus slave addresses (0111 000 and 0111 001) are reserved for the PCF8576D. The least significant bit of the slave address that a PCF8576D will respond to is defined by the level tied to its SA0 input. The PCF8576D is a write-only device and will not respond to a read access. Having two reserved slave addresses allows the following on the same I2C-bus:
* Up to 16 PCF8576Ds for very large LCD applications * The use of two types of LCD multiplex drive.
The I2C-bus protocol is shown in Figure 17. The sequence is initiated with a START condition (S) from the I2C-bus master which is followed by one of two possible PCF8576D slave addresses available. All PCF8576Ds whose SA0 inputs correspond to bit 0 of the slave address respond by asserting an acknowledge in parallel. This I2C-bus transfer is ignored by all PCF8576Ds whose SA0 inputs are set to the alternative level.
R/W slave address S
acknowledge by all addressed PCF8576Ds
acknowledge by A0, A1 and A2 selected PCF8576D only
S 011100A0AC
0 1 byte
COMMAND
A
DISPLAY DATA
A
P
n 1 byte(s)
n 0 byte(s) update data pointers and if necessary, subaddress counter
mdb078
Fig 17. I2C-bus protocol
After an acknowledgement, one or more command bytes follow, that define the status of each addressed PCF8576D. The last command byte sent is identified by resetting its most significant bit, continuation bit C, (see Figure 18). The command bytes are also acknowledged by all addressed PCF8576Ds on the bus.
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PCF8576D
Universal LCD driver for low multiplex rates
MSB C REST OF OPCODE
LSB
msa833
Fig 18. Format of command byte
After the last command byte, one or more display data bytes may follow. Display data bytes are stored in the display RAM at the address specified by the data pointer and the subaddress counter. Both data pointer and subaddress counter are automatically updated and the data directed to the intended PCF8576D device. An acknowledgement after each byte is asserted only by the PCF8576Ds that are addressed via address lines A0, A1 and A2. After the last display byte, the I2C-bus master asserts a STOP condition (P). Alternately a START may be asserted to restart an I2C-bus access.
7.17 Command decoder
The command decoder identifies command bytes that arrive on the I2C-bus. The commands available to the PCF8576D are defined in Table 7.
Table 7. Command Bit mode-set load-data-pointer device-select bank-select blink-select
[1] Not used.
Definition of PCF8576D commands Operation Code 7 C C C C C 6 1 0 1 1 1 5 0 P5 1 1 1 4
[1]
Reference 3 E P3 0 1 0 2 B P2 A2 0 A 1 M1 P1 A1 I BF1 0 M0 P0 A0 O BF0 Table 9 Table 10 Table 11 Table 12 Table 13
P4 0 1 1
All available commands carry a continuation bit C in their most significant bit position as shown in Figure 18. When this bit is set, it indicates that the next byte of the transfer to arrive will also represent a command. If this bit is reset, it indicates that the command byte is the last in the transfer. Further bytes will be regarded as display data (see Table 8).
Table 8. Bit 7 C bit description Symbol C 0 1 Value Description continue bit last control byte in the transfer; next byte will be regarded as display data control bytes continue; next byte will be a command too
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Universal LCD driver for low multiplex rates
Mode-set command bits description Symbol C E 0 1 Value 0, 1 10 Description see Table 8 fixed value unused display status disabled (blank)[1] enabled LCD bias configuration 0 1
1 3 1 2
Table 9. Bit 7 6, 5 4 3
2
B
bias bias
1 to 0
M[1:0] 01 10 11 00
LCD drive mode selection static; BP0 1:2 multiplex; BP0, BP1 1:3 multiplex; BP0, BP1, BP2 1:4 multiplex; BP0, BP1, BP2, BP3
[1]
The possibility to disable the display allows implementation of blinking under external control.
Table 10. Bit 7 6 5 to 0
Load-data-pointer command bits description Symbol C P[5:0] Value 0, 1 0 000000 to 100111 Description see Table 8 fixed value 6 bit binary value, 0 to 39; transferred to the data pointer to define one of forty display RAM addresses
Table 11. Bit 7 6 to 3 2 to 0
Device-select command bits description Symbol C A[2:0] Value 0, 1 1100 000 to 111 Description see Table 8 fixed value 3 bit binary value, 0 to 7; transferred to the subaddress counter to define one of eight hardware subaddresses
Table 12. Bit 7 6 to 2 1
Bank-select command bits description Symbol C I 0 1 Value 0, 1 11110 Description Static see Table 8 fixed value input bank selection; storage of arriving display data RAM bit 0 RAM bit 2 RAM bit 0 RAM bit 2 RAM bits 0 and 1 RAM bits 2 and 3 RAM bits 0 and 1 RAM bits 2 and 3 1:2 multiplex[1]
0
O 0 1
output bank selection; retrieval of LCD display data
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PCF8576D
Universal LCD driver for low multiplex rates
[1]
The bank-select command has no effect in 1:3 and 1:4 multiplex drive modes.
Table 13. Bit 7 6 to 3 2
Blink-select command bits description Symbol C A 0 1 Value 0, 1 1110 Description see Table 8 fixed value blink mode selection normal blinking[1] alternate RAM bank blinking[2] blink frequency selection 00 01 10 11 off 1 2 3
1 to 0
BF[1:0]
[1] [2]
Normal blinking is assumed when the LCD multiplex drive modes 1:3 or 1:4 are selected. Alternating RAM bank blinking does not apply in 1:3 and 1:4 multiplex drive modes.
7.18 Display controller
The display controller executes the commands identified by the command decoder. It contains the device's status registers and coordinates their effects. The display controller is also responsible for loading display data into the display RAM in the correct filling order.
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Universal LCD driver for low multiplex rates
8. Internal circuitry
VDD VDD
SA0
VSS VDD
VSS
CLK SCL VSS VDD VSS OSC
VSS VDD SDA
SYNC
VSS VDD
VSS
A0, A1 A2
VSS VLCD BP0, BP1, BP2, BP3 VSS VLCD VLCD
S0 to S39 VSS
mdb076
VSS
Fig 19. Device protection circuits
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PCF8576D
Universal LCD driver for low multiplex rates
9. Limiting values
CAUTION Static voltages across the liquid crystal display can build up when the LCD supply voltage (VLCD) is on while the IC supply voltage (VDD) is off, or vice versa. This may cause unwanted display artifacts. To avoid such artifacts, VLCD and VDD must be applied or removed together.
Table 14. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDD VLCD VI supply voltage LCD supply voltage input voltage on each of the pins CLK, SDA, SCL, SYNC, SA0, OSC, A0 to A2 on each of the pins S0 to S39, BP0 to BP3 Conditions Min -0.5 -0.5 -0.5 Max 6.5 +7.5 +6.5 Unit V V V
VO II IO IDD IDD(LCD) ISS Ptot Po Vesd
output voltage input current output current supply current LCD supply current ground supply current total power dissipation output power electrostatic discharge voltage
-0.5 -10 -10 -50 -50 -50 -
+7.5 +10 +10 +50 +50 +50 400 100 5000 200 1000 100 +150
V mA mA mA mA mA mW mW V V V mA C
HBM MM CDM
[1] [2] [3] [4] [5]
-65
Ilu Tstg
[1] [2] [3] [4] [5]
latch-up current storage temperature
Pass level; Human Body Model (HBM) according to JESD22-A114. Pass level; Machine Model (MM), according to JESD22-A115.
Pass level; Charged-Device Model (CDM), according to JESD22-C101. Pass level; latch-up testing, according to JESD78. According to the NXP store and transport conditions (document SNW-SQ-623) the devices have to be stored at a temperature of +5 C to +45 C and a humidity of 25 % to 75 %.
10. Static characteristics
Table 15. Static characteristics VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Supplies VDD VLCD
PCF8576D_7
Parameter supply voltage LCD supply voltage
Conditions
Min 1.8
[1]
Typ -
Max 5.5 6.5
Unit V V
2.5
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PCF8576D
Universal LCD driver for low multiplex rates
Table 15. Static characteristics ...continued VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol IDD IDD(LCD) Logic VP(POR) VIL power-on reset supply voltage LOW-level input voltage on pins CLK, SYNC, OSC, A0 to A2, SA0, SCL, SDA on pins CLK, SYNC, OSC, A0 to A2, SA0, SCL, SDA VOL = 0.4 V; VDD = 5 V on pins CLK and SYNC on pin SDA IOH(CLK) IL HIGH-level output current on pin CLK leakage current VOH = 4.6 V; VDD = 5 V VI = VDD or VSS; on pins CLK, SCL, SDA, A0 to A2 and SA0 VI = VDD
[5] [3][4]
Parameter supply current LCD supply current
Conditions fclk = 1536 Hz fclk = 1536 Hz
[2] [2]
Min 1.0 VSS
Typ 8 24 1.3 -
Max 20 60 1.6 0.3VDD
Unit A A V V
VIH
HIGH-level input voltage
0.7VDD
-
VDD
V
IOL
LOW-level output current
1 3 -1 -1
-
+1
mA mA mA A
IL(OSC) CI VO RO
leakage current on pin OSC input capacitance output voltage variation output resistance
-1 -100
[6]
-
+1 7 +100
A pF mV
LCD outputs on pins BP0 - BP3 and S0 - S39 VLCD = 5 V on pins BP0 to BP3 on pins S0 to S39
[1] [2] [3] [4] [5] [6] VLCD > 3 V for 13 bias. LCD outputs are open-circuit; inputs at VSS or VDD; external clock with 50 % duty factor; I2C-bus inactive. When tested, I2C pins SCL and SDA have no diode to VDD and may be driven to the VI limiting values given in Table 14 (see Figure 19 too). Propagation delay of driver between clock (CLK) and LCD driving signals. Periodically sampled, not 100 % tested. Outputs measured one at a time.
-
1.5 6.0
-
k k
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11. Dynamic characteristics
Table 16. Dynamic characteristics VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Clock fclk(int) fclk(ext) tclk(H) tclk(L) internal clock frequency external clock frequency HIGH-level clock time LOW-level clock time
[1]
Parameter
Conditions
Min 1440 960 60 60 1
Typ 1536 30 -
Max 2640 2640 30
Unit Hz Hz s s ns s s
Synchronization tPD(SYNC_N) SYNC propagation delay tSYNC_NL tPD(drv) I2C-bus[3] Pin SCL fSCL tLOW tHIGH Pin SDA tSU;DAT tHD;DAT tBUF tSU;STO tHD;STA tSU;STA tr tf Cb tw(spike)
[1] [2] [3]
SYNC LOW time driver propagation delay VLCD = 5 V
[2]
-
SCL clock frequency LOW period of the SCL clock HIGH period of the SCL clock data set-up time data hold time bus free time between a STOP and START condition set-up time for STOP condition hold time (repeated) START condition set-up time for a repeated START condition rise time of both SDA and SCL signals fSCL = 400 kHz fSCL < 125 kHz fall time of both SDA and SCL signals capacitive load for each bus line spike pulse width on the I2C-bus
1.3 0.6 100 0 1.3 0.6 0.6 0.6 -
-
400 0.3 1.0 0.3 400 50
kHz s s ns ns s s s s s s s pF ns
Pins SCL and SDA
Typical output duty factor: 50 % measured at the CLK output pin. Not tested in production. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an input voltage swing of VSS to VDD.
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Universal LCD driver for low multiplex rates
1 / fCLK tclk(H) CLK tclk(L) 0.7 VDD 0.3 VDD
SYNC tPD(SYNC_N) tSYNC_NL
0.7 VDD 0.3 VDD
0.5 V BP0 to BP3, and S0 to S39 tPD(drv) (VDD = 5 V) 0.5 V
001aai163
Fig 20. Driver timing waveforms
SDA
tBUF
tLOW
tf
SCL
tHD;STA
tr
tHD;DAT
tHIGH
tSU;DAT
SDA
tSU;STA tSU;STO
mga728
Fig 21. I2C-bus timing waveforms
PCF8576D_7
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PCF8576D
Universal LCD driver for low multiplex rates
12. Application information
12.1 Cascaded operation
In large display configurations, up to 16 PCF8576Ds can be differentiated on the same I2C-bus by using the 3-bit hardware subaddresses (A0, A1 and A2) and the programmable I2C-bus slave address (SA0).
Table 17. Cluster 1 Addressing cascaded PCF8576D Bit SA0 0 Pin A2 0 0 0 0 1 1 1 1 2 1 0 0 0 0 1 1 1 1 Pin A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Pin A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Device 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
PCF8576Ds connected in cascade are synchronized to allow the backplane signals from only one device in the cascade to be shared. This arrangement is cost-effective in large LCD applications since the backplane outputs of only one device need to be through-plated to the backplane electrodes of the display. The other cascaded PCF8576Ds contribute additional segment outputs but their backplane outputs are left open-circuit (see Figure 22). All PCF8576Ds connected in cascade are correctly synchronized by the SYNC signal. This synchronization is guaranteed after the power-on reset. The only time that SYNC is likely to be needed is if synchronization is lost accidentally, for example, by noise in adverse electrical environments, or if the LCD multiplex drive mode is changed in an application using several cascaded PCF8576Ds, as the drive mode cannot be changed on all of the cascaded devices simultaneously. SYNC can be either an input or an output signal; a SYNC output is implemented as an open-drain driver with an internal pull-up resistor. The PCF8576D asserts SYNC at the start of its last active backplane signal and monitors the SYNC line at all other times. If cascade synchronization is lost, it is restored by the first PCF8576D to assert SYNC. The timing relationship between the backplane waveforms and the SYNC signal for each LCD drive mode is shown in Figure 23.
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Universal LCD driver for low multiplex rates
The contact resistance between the SYNC on each cascaded device must be controlled. If the resistance is too high, the device is not able to synchronize properly; this is particularly applicable to chip-on-glass applications. The maximum SYNC contact resistance allowed for the number of devices in cascade is given in Table 18.
Table 18. 2 3 to 5 6 to 10 10 to 16 SYNC contact resistance Maximum contact resistance 6 k 2.2 k 1.2 k 700
Number of devices
The PCF8576D can be cascaded with the PCF8562, the PCF8533 or the PCF8534A. This allows optimal drive selection for a given number of pixels to display. Figure 20 and Figure 21 show the timing of the synchronization signals.
VDD 6 SDA 1, 58, 59 SCL 2, 3 SYNC CLK 4
VLCD 13
40 segment drives
LCD PANEL (up to 2560 elements)
PCF8576DU
BP0 to BP3 (open-circuit)
5 OSC 7 8 A0 VLCD VDD R tr 2CB
9
10 11 12 A1 A2 SA0 VSS
V DD
V
LCD
40 segment drives
HOST MICROPROCESSOR/ MICROCONTROLLER
6 13 SDA 1, 58, 59 SCL 2, 3 SYNC 4 PCF8576DU CLK 5 OSC 7 8 9 A1 10 A2 11 12
4 backplanes
BP0 to BP3
mdb077
VSS
A0
SA0 VSS
Fig 22. Cascaded PCF8576D configuration
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Universal LCD driver for low multiplex rates
Tfr =
1 ffr
BP0
SYNC
(a) static drive mode.
BP0 (1/2 bias)
BP0 (1/3 bias)
SYNC
(b) 1:2 multiplex drive mode.
BP0 (1/3 bias)
SYNC
(c) 1:3 multiplex drive mode.
BP0 (1/3 bias)
SYNC
(d) 1:4 multiplex drive mode.
mgl755
Fig 23. Synchronization of the cascade for the various PCF8576D drive modes
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Universal LCD driver for low multiplex rates
13. Package outline
TQFP64: plastic thin quad flat package; 64 leads; body 10 x 10 x 1.0 mm SOT357-1
c
y X A 48 49 33 32 ZE
e E HE A wM pin 1 index bp 17 1 16 ZD bp D HD wM B vM B vM A detail X Lp L A2 A 1 (A 3)
64
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.2 A1 0.15 0.05 A2 1.05 0.95 A3 0.25 bp 0.27 0.17 c 0.18 0.12 D (1) 10.1 9.9 E (1) 10.1 9.9 e 0.5 HD HE L 1 Lp 0.75 0.45 v 0.2 w 0.08 y 0.1 Z D(1) Z E(1) 1.45 1.05 1.45 1.05 7 o 0
o
12.15 12.15 11.85 11.85
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT357-1 REFERENCES IEC 137E10 JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 00-01-19 02-03-14
Fig 24. Package outline SOT357-1 (TQFP64)
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PCF8576D
Universal LCD driver for low multiplex rates
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm
SOT364-1
D
E
A
X
c y HE vMA
Z
56
29
Q A2 A1 pin 1 index Lp L (A 3) A
1
e bp wM
28
detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions). UNIT mm A max. 1.2 A1 0.15 0.05 A2 1.05 0.85 A3 0.25 bp 0.28 0.17 c 0.2 0.1 D (1) 14.1 13.9 E (2) 6.2 6.0 e 0.5 HE 8.3 7.9 L 1 Lp 0.8 0.4 Q 0.50 0.35 v 0.25 w 0.08 y 0.1 Z 0.5 0.1 8 o 0
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT364-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Fig 25. Package outline SOT364-1 (TSSOP56)
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14. Bare die outline
Wire bond die; 59 bonding pads; 2.26 x 2.01 x 0.38 mm PCF8576DU/DA
D
(4)
A 22
35
21 36
e
x
0
E 0 y
X
51
9
C2
52
59 1
8
C1
P4
P3
P2 P1 0 Dimensions Unit mm max nom min A 0.38 D 2.26 E 2.01 0.072 e(3) P1(1) 0.09 P2(2) 0.08 P3(1) P4(2) 0.5 scale 1 mm detail X
0.066 0.056
Notes 1. Pad size 2. Passivation opening 3. Dimension not drawn to scale 4. Marking code: PC8576D-2 Outline version PCF8576DU/DA References IEC JEDEC JEITA European projection
pcf8576du_da_do
Issue date 08-10-20 08-12-10
Fig 26. Bare die outline PCF8576DU/DA/2
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Universal LCD driver for low multiplex rates
Bare die; 59 bumps; 2.26 x 2.01 x 0.40 mm
PCF8576DU/2DA
D
(2)
35
22
21 36
e
Y
x
0
E 0 y
51
9
C2
52 X
59 1
8
C1
L
b detail X
A
A2
A1
0 Dimensions Unit mm max nom min A 0.40 A1 A2 b D 2.26 E 2.01 0.072 e(1) L 0.077
0.5 scale
1 mm
detail Y
0.015 0.381 0.052
Notes 1. Dimension not drawn to scale 2. Marking code: PC8576D-2 Outline version PCF8576DU/2DA References IEC JEDEC JEITA European projection
pcf8576du_2da_do
Issue date 08-10-23 08-12-10
Fig 27. Bare die outline PCF8576DU/2DA/2
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Table 19. Bonding pad location for PCF8576DUx All x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip (see Figure 4, Figure 26 and Figure 27). Symbol SDA SCL SCL SYNC CLK VDD OSC A0 A1 A2 SA0 VSS VLCD BP0 BP2 BP1 BP3 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21
PCF8576D_7
Pad 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
X (m) -34.38 109.53 181.53 365.58 469.08 577.08 740.88 835.83 1005.48 1005.48 1005.48 1005.48 1005.48 1005.48 1005.48 1005.48 1005.48 1005.48 1005.48 1005.48 1005.48 347.22 263.97 180.72 97.47 14.22 -69.03 -152.28 -235.53 -318.78 -402.03 -485.28 -568.53 -651.78 -735.03 -1005.5 -1005.5 -1005.5 -1005.5
Y (m) -876.6 -876.6 -876.6 -876.6 -876.6 -876.6 -876.6 -876.6 -630.9 -513.9 -396.9 -221.4 10.71 156.51 232.74 308.97 385.2 493.2 565.2 637.2 709.2 876.6 876.6 876.6 876.6 876.6 876.6 876.6 876.6 876.6 876.6 876.6 876.6 876.6 876.6 625.59 541.62 458.19 374.76
Description I2C-bus serial data input/output I2C-bus serial clock input cascade synchronization input/output external clock input/output supply voltage internal oscillator enable input subaddress inputs
I2C-bus address input; bit 0 ground supply voltage LCD supply voltage LCD backplane outputs
LCD segment outputs
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Table 19. Bonding pad location for PCF8576DUx ...continued All x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip (see Figure 4, Figure 26 and Figure 27). Symbol S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 S38 S39 SDA SDA Pad 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 X (m) -1005.5 -1005.5 -1005.5 -1005.5 -1005.5 -1005.5 -1005.5 -1005.5 -1005.5 -1005.5 -1005.5 -1005.5 -735.03 -663.03 -591.03 -519.03 -447.03 -375.03 -196.38 -106.38 Y (m) 291.33 207.9 124.47 41.04 -42.39 -125.8 -209.3 -292.7 -376.1 -459.5 -543 -625.6 -876.6 -876.6 -876.6 -876.6 -876.6 -876.6 -876.6 -876.6 I2C-bus serial data input/output Description LCD segment outputs
Table 20. Alignment marks All x/y coordinates represent the position of the center of each alignment mark with respect to the center (x/y = 0) of the chip (see Figure 4, Figure 26 and Figure 27). Symbol C1 C2 X (m) 930.42 -829.98 Y (m) -870.3 -870.3
15. Handling information
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be completely safe you must take normal precautions appropriate to handling MOS devices; see JESD625-A and/or IEC61340-5.
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16. Packing information
16.1 Tray information
x
G H
1,1 2,1
A
C
y
x,1
D
1,2
B
F
1,y
x,y
E
mce404
Fig 28. Tray details Table 21. Symbol A B C D E F G H x y Tray dimensions (see Figure 28) Description pocket pitch in x direction pocket pitch in y direction pocket width in x direction pocket width in y direction tray width in x direction tray width in y direction cut corner to pocket 1.1 center cut corner to pocket 1.1 center number of pockets, x direction number of pockets, y direction Value 5.59 6.35 3.16 3.16 50.8 50.8 5.83 6.35 8 7 Unit mm mm mm mm mm mm mm mm -
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PC8576D
mdb080
Fig 29. Tray alignment
16.2 Carrier tape information
4 A0 K0
pin 1 index
W
B0
P1 direction of feed
001aaj314
Fig 30. Tape details Table 22. Symbol A0 B0 K0 P1 W Carrier tape dimensions Description pocket width in x direction pocket width in y direction pocket height sprocket hole pitch tape width in y direction Value 8.6 14.5 1.8 12 24 Unit mm mm mm mm mm
PCF8576D_7
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17. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
17.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
17.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering
17.3 Wave soldering
Key characteristics in wave soldering are:
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities
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17.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 31) than a SnPb process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 23 and 24
Table 23. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 24. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 31.
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temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 31. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
18. Soldering of WLCSP packages
18.1 Introduction to soldering WLCSP packages
This text provides a very brief insight into a complex technology. A more in-depth account of soldering WLCSP (Wafer Level Chip-Size Packages) can be found in application note AN10439 "Wafer Level Chip Scale Package" and in application note AN10365 "Surface mount reflow soldering description". Wave soldering is not suitable for this package. All NXP WLCSP packages are lead-free.
18.2 Board mounting
Board mounting of a WLCSP requires several steps: 1. Solder paste printing on the PCB 2. Component placement with a pick and place machine 3. The reflow soldering itself
18.3 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 32) than a PbSn process, thus reducing the process window
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* Solder paste printing issues, such as smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature), and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic) while being low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 24
Table 25. Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 32.
temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 32. Temperature profiles for large and small components
For further information on temperature profiles, refer to application note AN10365 "Surface mount reflow soldering description".
18.3.1 Stand off
The stand off between the substrate and the chip is determined by:
* The amount of printed solder on the substrate * The size of the solder land on the substrate
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* The bump height on the chip
The higher the stand off, the better the stresses are released due to TEC (Thermal Expansion Coefficient) differences between substrate and chip.
18.3.2 Quality of solder joint
A flip-chip joint is considered to be a good joint when the entire solder land has been wetted by the solder from the bump. The surface of the joint should be smooth and the shape symmetrical. The soldered joints on a chip should be uniform. Voids in the bumps after reflow can occur during the reflow process in bumps with high ratio of bump diameter to bump height, i.e. low bumps with large diameter. No failures have been found to be related to these voids. Solder joint inspection after reflow can be done with X-ray to monitor defects such as bridging, open circuits and voids.
18.3.3 Rework
In general, rework is not recommended. By rework we mean the process of removing the chip from the substrate and replacing it with a new chip. If a chip is removed from the substrate, most solder balls of the chip will be damaged. In that case it is recommended not to re-use the chip again. Device removal can be done when the substrate is heated until it is certain that all solder joints are molten. The chip can then be carefully removed from the substrate without damaging the tracks and solder lands on the substrate. Removing the device must be done using plastic tweezers, because metal tweezers can damage the silicon. The surface of the substrate should be carefully cleaned and all solder and flux residues and/or underfill removed. When a new chip is placed on the substrate, use the flux process instead of solder on the solder lands. Apply flux on the bumps at the chip side as well as on the solder pads on the substrate. Place and align the new chip while viewing with a microscope. To reflow the solder, use the solder profile shown in application note AN10365 "Surface mount reflow soldering description".
18.3.4 Cleaning
Cleaning can be done after reflow soldering.
19. Abbreviations
Table 26. Acronym CMOS CDM HBM ITO LCD LSB MM MSB MSL PCB
PCF8576D_7
Abbreviations Description Complementary Metal Oxide Semiconductor Charged-Device Model Human Body Model Indium Tin Oxide Liquid Crystal Display Least Significant Bit Machine Model Most Significant Bit Moisture Sensitivity Level Printed Circuit Board
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Universal LCD driver for low multiplex rates
Abbreviations ...continued Description Random Access Memory Root Mean Square Surface Mount Device Wafer Level Chip-Size Package
Table 26. Acronym RAM RMS SMD WLCSP
PCF8576D_7
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Universal LCD driver for low multiplex rates
20. Revision history
Table 27. Revision history Release date 20081218 Data sheet status Product data sheet Product data sheet Product specification Product specification Product specification Product specification Objective specification Change notice Supersedes PCF8576D_6 PCF8576D_5 PCF8576D_4 PCF8576D_3 PCF8576D_2 PCF8576D_1 Document ID PCF8576D_7 Modifications: PCF8576D_6 PCF8576D_5 PCF8576D_4 PCF8576D_3 PCF8576D_2 PCF8576D_1
*
Added tape and reel delivery form
20081202 20041222 20041008 20040617 20030623 20030401
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21. Legal information
21.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
21.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Bare die -- All die are tested on compliance with their related technical specifications as stated in this data sheet up to the point of wafer sawing and are handled in accordance with the NXP Semiconductors storage and transportation conditions. If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There are no post-packing tests performed on individual die or wafers. NXP Semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. Accordingly, NXP Semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. It is the responsibility of the customer to test and qualify their application in which the die is used. All die sales are conditioned upon and subject to the customer entering into a written die sale agreement with NXP Semiconductors through its legal department.
21.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
21.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V.
22. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
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Universal LCD driver for low multiplex rates
23. Contents
1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.4.1 7.4.2 7.4.3 7.4.4 7.5 7.5.1 7.5.2 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.16.1 7.16.2 7.16.3 7.16.4 7.16.5 7.16.6 7.16.7 7.17 7.18 8 9 10 11 12 12.1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 Functional description . . . . . . . . . . . . . . . . . . . 7 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 8 LCD bias generator. . . . . . . . . . . . . . . . . . . . . . 8 LCD voltage selector . . . . . . . . . . . . . . . . . . . . 9 LCD drive mode waveforms . . . . . . . . . . . . . . 11 Static drive mode . . . . . . . . . . . . . . . . . . . . . . 11 1:2 Multiplex drive mode . . . . . . . . . . . . . . . . . 12 1:3 Multiplex drive mode . . . . . . . . . . . . . . . . . 14 1:4 Multiplex drive mode . . . . . . . . . . . . . . . . . 15 Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Internal clock. . . . . . . . . . . . . . . . . . . . . . . . . . 16 External clock . . . . . . . . . . . . . . . . . . . . . . . . . 16 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Display register . . . . . . . . . . . . . . . . . . . . . . . . 16 Segment outputs. . . . . . . . . . . . . . . . . . . . . . . 16 Backplane outputs . . . . . . . . . . . . . . . . . . . . . 16 Display RAM . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Output bank selector. . . . . . . . . . . . . . . . . . . . 20 Input bank selector . . . . . . . . . . . . . . . . . . . . . 20 Subaddress counter . . . . . . . . . . . . . . . . . . . . 20 Blinker. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Characteristics of the I2C-bus . . . . . . . . . . . . . 22 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 START and STOP conditions . . . . . . . . . . . . . 22 System configuration . . . . . . . . . . . . . . . . . . . 22 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 23 I2C-bus controller . . . . . . . . . . . . . . . . . . . . . . 23 Input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 24 Command decoder . . . . . . . . . . . . . . . . . . . . . 25 Display controller . . . . . . . . . . . . . . . . . . . . . . 27 Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 28 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 29 Static characteristics. . . . . . . . . . . . . . . . . . . . 29 Dynamic characteristics . . . . . . . . . . . . . . . . . 31 Application information. . . . . . . . . . . . . . . . . . 33 Cascaded operation . . . . . . . . . . . . . . . . . . . . 33 13 14 15 16 16.1 16.2 17 17.1 17.2 17.3 17.4 18 18.1 18.2 18.3 18.3.1 18.3.2 18.3.3 18.3.4 19 20 21 21.1 21.2 21.3 21.4 22 23 Package outline . . . . . . . . . . . . . . . . . . . . . . . . Bare die outline . . . . . . . . . . . . . . . . . . . . . . . . Handling information . . . . . . . . . . . . . . . . . . . Packing information . . . . . . . . . . . . . . . . . . . . Tray information . . . . . . . . . . . . . . . . . . . . . . . Carrier tape information . . . . . . . . . . . . . . . . . Soldering of SMD packages . . . . . . . . . . . . . . Introduction to soldering. . . . . . . . . . . . . . . . . Wave and reflow soldering . . . . . . . . . . . . . . . Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . Soldering of WLCSP packages . . . . . . . . . . . Introduction to soldering WLCSP packages. . Board mounting . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . Stand off. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quality of solder joint . . . . . . . . . . . . . . . . . . . Rework . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cleaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 38 41 42 42 43 44 44 44 44 45 46 46 46 46 47 48 48 48 48 50 51 51 51 51 51 51 52
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 18 December 2008 Document identifier: PCF8576D_7

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